1. Field of the Invention
The present invention relates to a central processing unit (CPU), and more particularly to a circuit that supplies power to a CPU.
2. Background of the Related Art
An Advanced Configuration and Power Interface (ACPI) is an open system solution including interfaces to hardware, an operating system (OS), software and peripheral devices of a personal computer (PC). ACPI was developed by Intel Corporation, Microsoft Corporation and Toshiba Corporation to support an OS, motherboard hardware and peripheral devices (e.g., a CD-ROM, hard drive, etc.) of a PC such that they can communicate with one another in terms of power use.
A related art power management system can interrupt the supply of power to devices after the lapse of certain disable periods of the devices because it is based on a basic input/output system (BIOS). However, the main goal of the ACPI is to support an Operating System Directed Power Management (OSPM) such that the OS can manage all power activities to supply power to devices only when necessary.
The ACPI was published in 1996 and defined power states of a CPU as C0, C1, C2 and C3. The C0 is a normal state, C1 is a halt state, C2 is a stop-grant state, and C3 is a stop clock state.
In the C2 state, the CPU performs a small or minimum amount of activity such as a snooping operation for maintaining a cache relevance. In the C3 state, which is a deep sleep state, no external clock is supplied to the CPU, thereby causing all activities of the CPU, excluding a function of maintaining data stored in a cache memory in the CPU, to be stopped. As a result, power consumption in the C3 state is reduced still more as compared with a CPU in the C2 state. In this regard, ACPI is very useful to a portable system with a limited battery lifetime.
An Intel Mobile Voltage Positioning (IMVP) II is an advanced voltage rectification technique recently developed by Intel Corporation. The IMVP II adds a new power state C4, or a deeper sleep state, to the power states C0˜C3 predefined by the ACPI to lower a supply voltage to the CPU when the CPU is not in operation and further reduce power consumption.
FIG. 1 is a block diagram showing a scheme for supplying power to a CPU in a computer system. As shown in FIG. 1, a power supply 10 includes a power source 11, such as an alternating current (AC) adapter or battery, and a DC/DC converter 12 for converting a direct current (DC) voltage from the power source 11 into a DC voltage Vcore of a level appropriate to a CPU 20 and outputting the converted DC voltage Vcore to the CPU 20.
The DC/DC converter 12 receives information signals DEEPSLEEP and DEEPERSLEEP about a current power state of the CPU 20 provided from a south-bridge controller (not shown) and supplies a DC voltage of a level corresponding to the received information signals to the CPU 20. For example, where the power state of the CPU is C0, C1, C2 or C3, the DC/DC converter 12 converts the DC voltage Vcc (e.g., 3.3V) supplied from the power source 11 into a normal DC voltage (e.g., an AC adapter/battery mode: 1.15V/1.05V) and provides the converted normal DC voltage Vcore to the CPU 20.
When the CPU 20 is in the power states C0˜C3, the power state information signals DEEPSLEEP and DEEPERSLEEP are both low in level (i.e., logic ‘0’) or the signals are respectively high in level (i.e., logic ‘1’) and low in level. Alternatively, if the power state information signal DEEPERSLEEP is high in level (i.e., the power state of the CPU is C4), that is, if a predetermined period of time has elapsed from the C3 state, the DC/DC converter 12 converts the DC voltage Vcc supplied from the power source 11 into a low DC voltage Vcore (0.85V) and provides the converted low voltage Vcore to the CPU 20.
FIG. 2 is a circuit diagram showing an example of the DC/DC converter 12 in FIG. 1. As shown in FIG. 2, the DC/DC converter 12 includes a power supply controller 14 which may be, for example, SC1471 “Power Supply Controller for Portable Pentium® IV SpeedStep™ Processors”, available from SEMTECH Corporation. The power supply controller 14 is adapted to generate control signals in response to the power state information signals DEEPSLEEP and DEEPERSLEEP. The DC/DC converter 12 further includes an NMOS transistor MN1 having a current path formed between a supply voltage Vcc from the power source 11 and a node N1, and a gate is controlled in response to a control signal from the power supply controller 14. An NMOS transistor MN2 has a current path formed between the node N1 and a ground voltage VSS with a gate controlled in response to another control signal from the power supply controller 14. An inductor L1 and a resistor R1 are connected in series between the node N1 and an output terminal that outputs the converted DC voltage Vcore, and a capacitor C1 connected between the output terminal and the ground voltage VSS.
As described above, the DC/DC converter 12 supports a deeper sleep mode as well as a deep sleep mode. The DC/DC converter 12 and outputs the voltage (e.g., 0.85V) lower than the normal voltage (e.g., 1.15˜1.05V) in the deeper sleep mode.
FIG. 3 is a graph showing a load-based efficiency characteristic of the DC/DC converter 12 in FIG. 1. FIG. 4 is a graph showing the frequency of activity states of a general CPU in a portable computer.
As shown in FIG. 3, the DC/DC converter 12 is very low in power efficiency when an amount of load is less than a predetermined value. That is, the DC/DC converter 12 is poor in efficiency when the CPU 20 is in a low activity state such as the deep sleep mode or deeper sleep mode. When the CPU 20 is in the low activity state, the DC/DC converter 12 is low in efficiency because of various factors. First, power consumption of the power supply controller 14. Second, switching drive power to the transistors MN1 and MN2. Third, a loss caused by a drain to source resistance RDSCON when the transistors MN1 and MN2 are turned on. Fourth, a loss because of the feedback sense resistor R1 for power stabilization.
Further, as shown in FIG. 4, the CPU 20 is generally in the low activity state more frequently than in a high activity state. This is understood from the fact that a time required for a user to input keys, move a mouse or read information displayed on a monitor is longer than a CPU operating time when the user conducts a specific task using a computer system.
As described above, there is a need in the related art for a new power supply scheme that is not degraded in efficiency even when the CPU 20 is in the low activity state. The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.